DocumentCode
2240254
Title
Optimal wire-sizing formula under the Elmore delay model
Author
Chen, Chung-Ping ; Chen, Yao-Ping ; Wong, D.F.
Author_Institution
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
487
Lastpage
490
Abstract
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be the width of the wire at position x, O⩽x⩽L. We show that the optimal wire-sizing function that minimizes the El more delay through the wire as f(x)=ae-bx , where a>0 and b>0 are constants that can be computed an O(1) time. In the case where lower bound (L>0) and upper bound (U>0) on the wire widths are given, we show that the optimal wire-sizing function f(x) is a truncated version of ae-bx that can also be determined an O(1) time. Our wire-sizing formula can be iteratively applied to optimally size the wire segments in a routing tree
Keywords
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; Elmore delay model; VLSI; nonuniform wire-sizing; optimal wire-sizing formula; optimal wire-sizing function; Capacitance; Circuit optimization; Delay effects; Iterative algorithms; Permission; Routing; Runtime; Upper bound; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545625
Filename
545625
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