Title :
A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques
Author :
Tu, Steve Hung-Lung ; Yen, Chih-Hung
Author_Institution :
Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei
Abstract :
In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit
Keywords :
high-speed integrated circuits; logic design; multiplying circuits; high-speed Baugh-Wooley multiplier design; logic path unbalance; skew-tolerant domino techniques; static circuit; system clock skew; Adders; CMOS logic circuits; Central Processing Unit; Circuit simulation; Clocks; Design engineering; Latches; Logic circuits; Merging; Timing; Multiplier; clock skew; domino circuit; skew-tolerant domino; static circuit;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342059
