Formalizing certain tasks for processor architecture verification

Present day verification is a time consuming task. With processor architecture complexity increasing by the day, managing the complete verification process has become a major challenge. Besides, a small bug in the final product may ruin all the efforts. This problem has resulted in the popularity of verification and other related technologies. For example formal verification is now considered as an important part of any verification process. Similarly other technologies and methodologies are gaining acceptance. However, despite all these tools and technologies, verification still remains the main bottleneck and challenge in the overall process for the development of a modern processor. This problem can be looked from a different angle. We believe that a proper strategy is equally important for the verification efforts to succeed. The strategy will be easier once we formalize certain aspects of the process. This paper is an attempt to formalize some of the important aspects, ideas and methodologies towards the verification of processor architecture.