DocumentCode :
2243942
Title :
Exploiting Concurrency in System-on-Chip Verification
Author :
Xu, Justin ; Lim, Cheng-Chew
Author_Institution :
Adelaide Univ., SA
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
836
Lastpage :
839
Abstract :
System-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs. This is made possible by modelling transfers as active building blocks
Keywords :
automatic test pattern generation; integrated circuit design; system-on-chip; active building blocks; design verification; event-driven test-programs; system concurrency; system-on-chip verification; test generation; test quality; transfer-resource-graph; Australia; Automatic testing; Computer bugs; Concurrent computing; Design methodology; Formal verification; Software testing; System testing; System-on-a-chip; Very large scale integration; System-on-Chip; Test Generation; Verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342151
Filename :
4145523
Link To Document :
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