A 1.4 V 10-bit 20 MSPS pipelined A/D converter

Author

Choi, Hee Cheol ; Park, Ho-Jin ; Bae, Shin-Kyu ; Kim, Jae-Whui ; Chung, Philip

Author_Institution

ASIC Dev. Team, Samsung Electron. Co., Yongin, South Korea

Volume

1

fYear

2000

fDate

2000

Firstpage

439

Abstract

A 1.4 V 10-bit 20 MSPS pipelined analog-to-digital converter was implemented using 0.25 μm CMOS technology. The converter is based on low-voltage two-stage opamps and current reference generator for low-voltage operation. The current reference generator adopts a newly proposed dual-mode voltage booster that keeps the reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm² (1700 μm×1300 μm) and dissipates 43 mW and 20 MHz clock rate with a 1.4 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.59 LSB and ±0.68 LSB, respectively

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; pipeline processing; 0.25 micron; 1.4 V; 10 bit; 20 MHz; 43 mW; CMOS technology; current reference generator; die area; differential nonlinearity; dual-mode voltage booster; integral nonlinearity; low-voltage two-stage opamps; pipelined A/D converter; reference current; CMOS technology; Capacitors; Charge pumps; Circuits; Clocks; Costs; Frequency; Ring oscillators; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857125

Filename

857125