• DocumentCode
    22464
  • Title

    A 25-Gb/s 5-mW CMOS CDR/Deserializer

  • Author

    Jun Won Jung ; Razavi, Behzad

  • Author_Institution
    Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • Volume
    48
  • Issue
    3
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    684
  • Lastpage
    697
  • Abstract
    The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz jitter frequency.
  • Keywords
    CMOS logic circuits; clock and data recovery circuits; jitter; CMOS CDR-deserializer; bit rate 25 Gbit/s; charge-steering logic; frequency 5 MHz; half-rate clock-data recovery circuit; jitter frequency; jitter tolerance; power 5 mW; power consumption; receiver building block; serial links; size 65 nm; time 1.5 ps; transmitter building block; voltage 1 V; Clocks; Detectors; Jitter; Latches; Optical signal processing; Topology; Transistors; Charge steering; clock and data recovery; deserializer; phase detecter;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2013.2237692
  • Filename
    6416959
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=22464