DocumentCode
2247377
Title
An Efficient Self-Transposing Memory Structure for 32-bit Video Processors
Author
Bojnordi, Mahdi Nazm ; Sedaghati-Mokhtari, Naser ; Fatemi, Omid ; Hashemi, Mahmoud Reza
Author_Institution
Sch. of Electr. & Comput. Eng., Tehran Univ.
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1438
Lastpage
1441
Abstract
Many 2D data processing applications can be simplified and represented by use of 1D operations. Such tools, however, require applying both vertical and horizontal operations to the data blocks. The data transposing units is preferred to be used by the designers rather than applying individual operations for horizontal and vertical directions. Hence, designing a cost efficient and extendible transposing memory is a key issue for these applications. This paper proposes an efficient management strategy for using the SRAM modules in order to make a self-transposing memory architecture (STMA). In addition to its lower cost compared to flip-flop based buffers, the proposed architecture is more than 29% faster than usual SRAM based memory units. Simulations indicate that using the STMA in the H.264/AVC deblocking filter results in 60% speed improvement
Keywords
SRAM chips; coprocessors; video coding; 32 bit; H.264/AVC deblocking filter; SRAM modules; data transposing units; self-transposing memory structure; video processors; Automatic voltage control; Costs; Engines; Filters; Hardware; Memory architecture; Pixel; Random access memory; Signal processing algorithms; Switches; Self-Transposing memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342472
Filename
4145672
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