Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses

Author

Zhang, Qingli ; Wang, Jinxiang ; Ye, Yizheng

Author_Institution

Microelectron. Center, Harbin Inst. of Technol.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1611

Lastpage

1614

Abstract

The power consumption and propagation delay are two important issues for global on-chip buses in deep submicron system-on-chip design. And inter-wire coupling is a major source of the two issues. In this paper, we present a new bus encoding scheme for generic on-chip data buses that simultaneously reduces coupling power consumption and eliminates capacitive crosstalk. Experimental results indicate that our proposed scheme can provide about 21% bus power reduction on average while minimizing the crosstalk delay. Furthermore, we employ a bus-invert coding technique to improve the power efficiency of the proposed approach by up to 7.7%

Keywords

encoding; integrated circuit design; low-power electronics; system-on-chip; bus encoding scheme; capacitive crosstalk elimination; coupling power consumption reduction; crosstalk delay minimisation; generic on-chip data buses; low-power crosstalk avoidance encoding; propagation delay; Crosstalk; Data buses; Encoding; Energy consumption; Microelectronics; Parasitic capacitance; Power dissipation; Propagation delay; System-on-a-chip; Wires; coulping; encoding; low-power; on-chip bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342072

Filename

4145716