A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC

Author

Babaie, Masoud ; Movahedian, Hamid ; Bakhtiar, Mehrdad Sharif

Author_Institution

Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1768

Lastpage

1771

Abstract

In this paper, the systematic error due to interpolation in CMOS deep sub micron folding and interpolating ADC is studied and a closed form equation is presented to calculate the error as a function of interpolation coefficient, input voltage range and the number of input differential pairs. The amount of INL due to interpolation error can be considered as the lower bound for attainable INL of a specific ADC architecture. A case study for an 8_bit ADC is treated under consideration of different folding and interpolating factors. The trade off between power dissipation and ADC performance is characterized according to input stage characteristics

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; 8 bit; ADC architecture; CMOS deep submicron folding ADC; closed form equation; interpolating ADC; systematic error prediction; Analog-digital conversion; CMOS technology; Differential equations; Frequency conversion; Interpolation; Mean square error methods; Power dissipation; Sampling methods; Tail; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342160

Filename

4145754