Title :
Another Look at the Sequential Multiplier over Normal Bases
Author :
Chen, Zih-Heng ; Jing, Ming-Haw ; Truong, Trieu-Kien ; Chang, Yaotsu
Author_Institution :
Dept. of Inf. Eng., I-Shou Univ.
Abstract :
The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m), which can perform multiplication in m clock cycles for the normal basis. In this article, the authors propose a new architecture to carry out the sequential multiplier using normal basis. The time complexity in each cycle of this new multiplier is O(1) and the number of inputs is lower down to m+1, instead of 2m, which is the number needed for most previous multipliers. These merits make it easier to the VLSI implementation
Keywords :
VLSI; algebraic codes; digital arithmetic; VLSI implementation; finite fields; normal bases; sequential multiplier; Arithmetic; Clocks; Cryptography; Delay effects; Embedded system; Error correction codes; Galois fields; Hardware; Mathematics; Very large scale integration; VLSI implementation; finite fields; normal basis; sequential multiplier;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342168