A new and efficient approach for high-speed and very compact realization of Secure Hash Algorithm

We are proposing that the recently proposed cell-FPGA-like hybrid CMOS/nanodevice architecture is an optimum platform to realize encryption algorithms. Such circuits will combine a semiconductor-transistor (CMOS) stack and a two-level nanowire crossbar with nanoscale two-terminal nanodevices (programmable diodes) formed at each crosspoint. The basic modules of the Secure Hash Algorithm (SHA-512) have been designed using this architecture. In addition, using a custom set of design automation tools, quasi-optimum gate placing, routing and rerouting are provided for SHA-512 building blocks. It is shown that such a design results in a circuit which is defect tolerant, much faster and strikingly denser than its CMOS counterpart.