A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer time and more power consumption in testing. In this paper, we propose a novel hardware architecture base on "LBIST Controller" to reduce test application time and test power consumption. Give a test cubes for stuck-at faults contain unspecified bit generated by a sequential automatic test pattern generator (ATPG). Use our propose algorithm in section III can group test cubes to several section schemes. Then mapping to our propose hardware architecture in section II. While "Section Counter" is more then zero, scan in could through MUX and bypass the flip-flops in "Fixed Group". And we can save power consumption and test application time in this time. According to our simulation result, we reduce about 20% ~ 60% power consumption and 50% ~ 80% test application time in some ISCAS\´89 benchmarks