Performance and throughput assessment of the Motorola DSP96002 for real-time FIR filter implementations

Author

Richardson, A.O. ; Miramontes, G.

Author_Institution

Dept. of Electr. & Electron. Eng., California State Univ., Chico, CA, USA

fYear

1993

fDate

1-3 Nov 1993

Firstpage

1608

Abstract

The execution speed of the Motorola DSP96002 is assessed, by establishing the maximum number of taps of FIR filters that can be implemented in real time. Calculations using manufacturer supplied data yielded a theoretical value of 324 for maximum number of taps for real-time FIR. Real time measurements produced results of 325 for the maximum number of taps. This translates to the execution of an FIR kernel in (2N+24) clock cycles. The 96002 was run at 33.3 MHz, and the sampling rate was 48 kHz. Establishing such throughput limitations is crucial in time critical applications,

Keywords

digital filters; digital signal processing chips; frequency response; 33.3 MHz; 48 kHz; Motorola DSP96002; clock cycles; execution speed; real time measurements; real-time FIR filter; sampling rate; taps; Assembly; Availability; Clocks; Digital signal processing; Finite impulse response filter; Kernel; Manufacturing; Sampling methods; Signal processing; Signal sampling; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-4120-7

Type

conf

DOI

10.1109/ACSSC.1993.342342

Filename

342342