Title :
A pipelined Kalman filter architecture
Author :
Shanbhag, Naresh R. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Presented in the paper is a hardware-efficient pipelined Kalman filter architecture for recursive least-squares (RLS) identification. The proposed architecture is developed via the relaxed look-ahead technique. This technique results in an extremely low hardware overhead at the expense of a slightly degraded performance. The hardware overhead due to pipelining consists of only the pipelining latches and is therefore negligible. Convergence analysis and simulations indicate that the adaptation accuracy of the pipelined and serial architectures are identical. Speed-up of up to 15 is demonstrated via simulations. Finally, a folded architecture for a pipelined Kalman filter is presented. This folded architecture reduces the number of computational elements by half while still achieving substantial speed-up
Keywords :
Kalman filters; computational complexity; convergence; digital filters; least squares approximations; parallel architectures; parameter estimation; pipeline processing; PIPKAL; adaptation accuracy; convergence analysis; folded architecture; hardware overhead; performance; pipelined Kalman filter architecture; pipelined architecture; pipelining latches; recursive least-squares identification; relaxed look-ahead technique; serial architecture; speed-up time; Algorithm design and analysis; Analytical models; Computational modeling; Computer architecture; Convergence; Degradation; Digital signal processing; Equations; Hardware; Pipeline processing; Resonance light scattering; Signal processing algorithms; Throughput;
Conference_Titel :
Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-4120-7
DOI :
10.1109/ACSSC.1993.342377