DocumentCode
2252131
Title
A methodology for concurrent fabrication process/cell library optimization
Author
Lokanathan, Arun N. ; Brockman, Jay B. ; Renaud, John E.
Author_Institution
Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
825
Lastpage
830
Abstract
The paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield. The approach uses the Concurrent Subspace Optimization (CSSO) algorithm, which has been developed for general coupled, multidisciplinary optimization problems. An example is provided showing the application of the algorithm to optimizing a mixed analog/digital library on a CMOS process
Keywords
CMOS integrated circuits; circuit CAD; circuit optimisation; concurrent engineering; integrated circuit manufacture; CMOS process; CSSO algorithm; Concurrent Subspace Optimization; IC fabrication process; concurrent fabrication process/cell library optimization; mixed analog/digital library; multidisciplinary optimization problems; standard cell library; Algorithm design and analysis; CMOS process; Circuit optimization; Design engineering; Design optimization; Fabrication; Libraries; Optimization methods; Permission; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545685
Filename
545685
Link To Document