Average-case optimized transistor-level technology mapping of extended burst-mode circuits

Author

James, Kevin W. ; Yun, Kenneth Y.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1998

fDate

30 Mar-2 Apr 1998

Firstpage

70

Lastpage

79

Abstract

We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal performance for the average or common case

Keywords

asynchronous circuits; logic design; minimisation of switching nets; optimisation; 3D-map; Elmore delay analysis; automated method; average-case optimization; average-case optimized transistor-level technology mapping; burst-mode asynchronous controllers; extended burst-mode circuits; near-optimal decomposed generalized C-element implementations; near-optimal performance; Acceleration; Asynchronous circuits; Automatic control; Circuit synthesis; Decoding; Delay; Design optimization; Logic; Signal synthesis; Size control;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on

Conference_Location

San Deigo, CA

Print_ISBN

0-8186-8392-9

Type

conf

DOI

10.1109/ASYNC.1998.666495

Filename

666495