Title :
A single chip low power asynchronous implementation of an FFT algorithm for space applications
Author :
Hunt, B.W. ; Stevens, K.S. ; Suter, B.W. ; Gelosh, D.S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA
fDate :
30 Mar-2 Apr 1998
Abstract :
A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed by a discussion of circuit design parameters specifically those relevant to space applications. A survey of this application specific architecture is included with a detailed look at the design of the complex-valued Booth multiplier to demonstrate the design methodology of this project. Finally, simulation results based on layout extractions are presented and an outline for future work is given
Keywords :
asynchronous circuits; fast Fourier transforms; integrated circuit design; logic design; Booth multiplier; FFT processor; application specific architecture; asynchronous; circuit design parameters; fixed point; space applications; Application software; Computer architecture; Design methodology; Discrete Fourier transforms; Equations; Hardware; Pipeline processing; Signal processing algorithms; Space technology; Throughput;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on
Conference_Location :
San Deigo, CA
Print_ISBN :
0-8186-8392-9
DOI :
10.1109/ASYNC.1998.666507