Title :
POSA: Power-state-aware buffered tree construction
Author :
Jiang, Iris Hui-Ru ; Wu, Ming-Hua
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Buffering without considering power states in multiple supply voltage designs may result in infeasible signals. POSA is the first work to handle this issue. Our buffered tree guarantees feasibility all the times, even when some parts of the design shut down. This feature is one of the key techniques to fulfill power-aware design methodology.
Keywords :
buffer circuits; network synthesis; power aware computing; POSA; multiple supply voltage; power-aware design; power-state-aware buffered tree; Circuits; Design engineering; Design methodology; Iris; Low voltage; Power engineering and energy; Signal design; Timing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117870
