Techno-economic analysis of competing IC packaging protocols

Author

Hannibal, Theodore A., III ; Capote, M. Al

Author_Institution

IBIS Associates, Inc, Waltham, MA, USA

fYear

2002

fDate

2002

Firstpage

426

Lastpage

428

Abstract

Comparing alternative packaging technologies is a complex task, involving prioritization of cost, performance, and business strategy issues. This paper focuses on one portion of the decision-making equation - cost. Using a tool for assessing the manufacturing costs of electronic packaging, cost outlook scenarios for three advanced packaging technologies are analyzed and compared. The technologies are flip-chip-on-board (FCOB), wafer-scale chip-scale packaging (WSCSP), and a new wafer-scale-applied underfill technology called wafer pre-encapsulation. Using Technical Cost Modeling the paper tracks and examines the costs for the three implementations, starting from wafer-level through IC packaging to board placement. Manufacturing cost sensitivity is examined for a variety of manufacturing conditions and results are presented.

Keywords

chip scale packaging; encapsulation; flip-chip devices; integrated circuit economics; integrated circuit packaging; IC packaging; flip-chip-on-board technology; manufacturing cost; technical cost modeling; techno-economic analysis; wafer pre-encapsulation; wafer-scale chip-scale packaging; wafer-scale underfill technology; Chip scale packaging; Costs; Decision making; Electronics packaging; Equations; Integrated circuit modeling; Integrated circuit packaging; Manufacturing; Protocols; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International

Print_ISBN

0-7803-7301-4

Type

conf

DOI

10.1109/IEMT.2002.1032794

Filename

1032794