Title :
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
Author :
Zhu, Jun ; Sander, Ingo ; Jantsch, Axel
Author_Institution :
R. Inst. of Technol., Stockholm, Sweden
Abstract :
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.
Keywords :
Pareto optimisation; field programmable gate arrays; media streaming; reconfigurable architectures; resource allocation; scheduling; CPU-FPGA platform; Gecode; Pareto efficient design; constraint based application allocation; design Pareto-point calculation flow; multidimensional optimization; optimized buffer requirement; public domain solver; reconfiguration analysis; runtime reconfigurable streaming application; scheduling; software-hardware implementation cost; Application software; Cost function; Design methodology; Design optimization; Field programmable gate arrays; Hardware; Pareto analysis; Pareto optimization; Runtime; Throughput;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5456962