Title :
A fast-locking and wide-range reversible SAR DLL
Author :
Wang, Lei ; Liu, Leibo ; Chen, Hongyi
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
A reversible successive approximation register (RSAR) controlled all-digital delay-locked loop (ADDLL) is proposed to achieve fast-lock and wide range operation. The modified binary search algorithm of RSAR scheme is presented. With improved RSAR control-circuits, it could achieve adaptive bandwidth in wide range operation and eliminate the dead lock problem of conventional SAR DLL. The maximal lock-in cycles are reduced down to 42 for the 11-bit RSAR DLL, and its frequency range is from 30 MHz to 1 GHz in post layout simulation. The layout is done in SMIC 0.13 mum CMOS technology, and an active area of 0.2 mm by 0.1 mm is occupied.
Keywords :
CMOS integrated circuits; UHF integrated circuits; VHF circuits; delay lock loops; integrated circuit layout; semiconductor process modelling; SMIC CMOS technology; all-digital delay-locked loop; binary search algorithm; dead lock problem; fast locking; frequency 30 MHz to 1 GHz; lock-in cycles; post layout simulation; reversible SAR DLL; reversible successive approximation register; size 0.13 mum; CMOS technology; Clocks; Control systems; Delay effects; Delay lines; Detectors; Frequency; Jitter; Laboratories; Phase locked loops;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117925
