ESD latency effects in CMOS integrated circuits

Author

Greason, W.D. ; Kucerovsky, Z. ; Chum, K.

Author_Institution

Dept. of Electr. Eng., Univ. of Western Ontario, London, Ont., Canada

fYear

1990

fDate

7-12 Oct. 1990

Firstpage

876

Abstract

Measurements were performed on two types of commercially available and custom-made CMOS integrated circuits to investigate the latent mode of failure due to ESD (electrostatic discharge). The current injection test method is used for both polarities of discharge. Test parameters studied include threshold failure, constant amplitude multiple stress, step stress, and the stress hardening effect. Statistical analyses of the results demonstrate the presence of latent failure in CMOS integrated circuits due to ESD. The work is used to further expand a charge injection model for latent failures.<>

Keywords

CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit testing; CMOS integrated circuits; ESD latency effects; constant amplitude multiple stress; current injection test method; discharge polarity; electrostatic discharge; step stress; stress hardening effect; threshold failure; CMOS integrated circuits; Circuit testing; Delay; Electrostatic discharge; Electrostatic measurements; Integrated circuit measurements; Performance evaluation; Semiconductor device modeling; Statistical analysis; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Industry Applications Society Annual Meeting, 1990., Conference Record of the 1990 IEEE

Conference_Location

Seattle, WA, USA

Print_ISBN

0-87942-553-9

Type

conf

DOI

10.1109/IAS.1990.152287

Filename

152287