DocumentCode
2255683
Title
Accurate timed RTOS model for transaction level modeling
Author
Hwang, Yonghyun ; Schirner, Gunar ; Abdi, Samar ; Gajski, Daniel G.
Author_Institution
CECS, Univ. of California, Irvine, CA, USA
fYear
2010
fDate
8-12 March 2010
Firstpage
1333
Lastpage
1336
Abstract
In this paper, we present an accurate timed RTOS model within transaction level models (TLMs). Our RTOS model, implemented on top of system level design language (SLDL), incorporates two key features: RTOS behavior model and RTOS overhead model. The RTOS behavior model provides dynamic scheduling, inter-process communication (IPC), and external communication for timing annotated user applications. While the RTOS behavior model is running, all RTOS events, such as context switch and interrupt handling, are passed to RTOS over-head model to adopt the overhead during system execution. Our RTOS overhead model has processor- and RTOS-specific pre-characterized overhead information to provide cycle approximate estimation. We demonstrate the applicability of our model using a multi-core platform executing a JPEG encoder. Experimental results show that the proposed RTOS model provides the high accuracy, 7% off compared to on-board measurements while simulating at speeds close to the reference C code.
Keywords
scheduling; transaction processing; JPEG encoder; RTOS behavior model; RTOS speciflc precharacterized overhead information; accurate timed RTOS model; cycle approximate estimation; dynamic scheduling; interprocess communication; multicore platform; system level design language; transaction level modeling; Application software; Context modeling; Delay estimation; Dynamic scheduling; Performance analysis; Scalability; Software performance; Switches; System-level design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4244-7054-9
Type
conf
DOI
10.1109/DATE.2010.5457015
Filename
5457015
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