Universal read/write buffer for multiprocessor cache coherency schemes

There are many publications in the area of cache coherence for multiprocessor systems as shared memory has proved to be a very effective approach to high speed performance. However, most of the works reported are limited to applications of multiprocessor systems using a single protocol. As the complexity of the multiprocessor system increases, the demand for using mixed computers in one system is more and more pronounced. We present the design and implementation of universal read/write buffer which supports multiprocessor cache coherence of different protocols. An analysis of the approach is made, and the hardware and algorithm are discussed in detail. The complete design has been simulated successfully in VHDL. Our analysis shows that, for given system parameters, the performance of the cache system is improved by more than 200% if the universal buffer is used