Title :
A novel N-bit SAR implementation for All-Digital DLL circuits
Author :
El-Shafie, Al-Hussein A. ; Habib, S.E.-D.
Author_Institution :
Fac. of Eng., Cairo Univ., Cairo, Egypt
Abstract :
A novel implementation of the N-bit Successive Approximation Register (SAR) Delay Locked Loop (DLL) is proposed with a significantly reduced hardware overhead relative to the conventional approach. The hardware overhead for the proposed 2-bit SAR scheme is only 25% of that for the conventional 2-bit SAR scheme. In this work, a complete All-Digital DLL (ADDLL) design implementing the proposed 2-bit scheme is developed. All design units are first described in Verilog, and then mapped to silicon using the IBM 0.13μm Artisan standard cell library. The proposed design has an active area of 0.009mm2 and can operate from 140MHz to 800MHz with a locking time of six input clock cycles only.
Keywords :
approximation theory; delay lock loops; digital circuits; hardware description languages; integrated circuit design; 2-bit SAR scheme; Artisan standard cell library; N-bit successive approximation register delay locked loop; Verilog; all-digital DLL circuit design; frequency 140 MHz to 800 MHz; size 0.13 mum; word length 2 bit; Added delay; Clocks; Decoding; Delay; Delay lines; Hardware; Solid state circuits; ADDLL; DLL; N-bit successive approximation register (N-bit SAR); fast-locking;
Conference_Titel :
Microelectronics (ICM), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-61284-149-6
DOI :
10.1109/ICM.2010.5696179
