On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-mum standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.