• DocumentCode
    2260065
  • Title

    IP routing processing with graphic processors

  • Author

    Mu, Shuai ; Zhang, Xinya ; Zhang, Nairen ; Lu, Jiaxin ; Deng, Yangdong Steve ; Zhang, Shu

  • Author_Institution
    Tsinghua Univ., Beijing, China
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    93
  • Lastpage
    98
  • Abstract
    Throughput and programmability have always been the central, but generally conflicting concerns for modern IP router designs. Current high performance routers depend on proprietary hardware solutions, which make it difficult to adapt to ever-changing network protocols. On the other hand, software routers offer the best flexibility and programmability, but could only achieve a throughput one order of magnitude lower. Modern GPUs are offering significant computing power, and its data-parallel computing model well matches the typical patterns of packet processing on routers. Accordingly, in this research we investigate the potential of CUDA-enabled GPUs for IP routing applications. As a first step toward exploring the architecture of a GPU based software router, we developed GPU solutions for a series of core IP routing applications such as IP routing table lookup and pattern match. For the deep packet inspection application, we implemented both a Bloom-filter based string matching algorithm and a finite automata based regular expression matching algorithm. A GPU based routing table lookup solution is also proposed in this work. Experimental results proved that GPU could accelerate the routing processing by one order of magnitude. Our work suggests that, with proper architectural modifications, GPU based software routers could deliver significant higher throughput than previous CPU based solutions.
  • Keywords
    IP networks; routing protocols; string matching; table lookup; telecommunication network routing; Bloom filter; IP routing processing; IP routing table lookup; data-parallel computing model; graphic processors; hardware solutions; packet inspection application; packet processing; pattern matching; software routers; string matching algorithm; toward; Application software; Computer architecture; Graphics; Hardware; Inspection; Pattern matching; Protocols; Routing; Table lookup; Throughput; Bloom filter; CUDA; DFA; Deep packet inspection; GPU; router; table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5457229
  • Filename
    5457229