Title :
An SoC integrating an H.264 encoder with an ISP
Author :
Kim, Eung Sup ; Seongyoon Kim ; Hyun, GyoungHwan ; Jung, Jinsu ; Rhee, Chae Eun ; Jin, Yongseok ; Lee, Hyuk-Jae
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Abstract :
The SoC presented in this paper integrates an H.264 encoder with an ISP (image signal processor). It is currently implemented in an FPGA and processes an HD-size (1280 times 720) image at the speed of 15 fps with the operating clock frequency of 50 MHz. In the presented demo system, a Bayer input from a CMOS image is given to the FPGA and the output stream is transmitted through an USB transceiver to a PC that decodes and displays the H.264 stream.
Keywords :
CMOS integrated circuits; field programmable gate arrays; system-on-chip; video coding; Bayer input; CMOS image; FPGA; H.264 encoder; ISP; SoC; USB transceiver; clock frequency; frequency 50 MHz; image signal processor; Automatic voltage control; Color; Decoding; Displays; Field programmable gate arrays; Hardware; Image sensors; Signal processing; Streaming media; Universal Serial Bus;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118167
