Minimising buffer latency through optimum transistor p-to-n ratio scaling

This paper establishes, in the case of CMOS buffer chains, that along with an optimum scaling factor there exists an equivalent optimum P-to-N transistor ratio which minimises latency. An optimum triple-point of buffer number, P-to-N ratio and scaling factor is identified which provides a process-specific absolute minimum latency. It is further determined that for any number of buffers, the corresponding optimum P-to-N transistor ratio and optimum buffer scaling factor can be calculated simultaneously, through numerical approximation of the points of intersection of two transcendental equations.