Title :
Testing for missing-gate faults in reversible circuits
Author :
Hayes, John P. ; Polian, Ilia ; Becker, Bernd
Author_Institution :
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Abstract :
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.
Keywords :
built-in self test; circuit simulation; design for testability; fault location; integrated circuit testing; logic testing; quantum gates; N-gate k-CNOT circuit; controllable NOT gates; design-for-test method; fault testing; k-CNOT circuits; k-CNOT gates; logical reversibility; missing-gate faults; quantum circuits; reversible circuits; stuck-at model; test vectors; Application software; Circuit faults; Circuit simulation; Circuit testing; Computer architecture; Design for testability; Electrical fault detection; Fault detection; Laboratories; Quantum computing; Reversible circuits; design for test; fault models; missing gate faults; quantum circuits;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.84