Title :
Delay modelling and optimization of BiCMOS buffer circuits
Author :
Esonu, M.O. ; Al-Khalili, D. ; Al-Khalili, A.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada
Abstract :
In this work the analytical delay expressions for BiCMOS buffer circuits are presented. The equations contain device geometrical and other process parameters, and can be used to calculate the rise and fall transient responses for a buffer circuit. The influence of the device parameters on switching speed is investigated. The delay expressions have been used in the design and optimization of BiCMOS buffer circuits
Keywords :
BiCMOS logic circuits; buffer circuits; circuit analysis computing; circuit optimisation; delays; integrated circuit modelling; logic CAD; transient response; BiCMOS buffer circuits; delay modelling; optimization; switching speed; transient responses; Analytical models; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; Capacitance; Circuit simulation; Delay; Design optimization; MOSFETs; Military computing;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.342983
