Title :
Efficient template generation for instruction-based self-test of processor cores
Author :
Kambe, Kazuko ; Inoue, Michiko ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science City, Japan
Abstract :
This paper presents a method of template generation for instruction-based self-test of processor cores. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and propagation of test responses for a module under test (MUT). In order to justify value of MUT inputs, we introduce a concept of adjacent registers of the MUT that makes it possible to consider input spaces of the MUT determined by signals from other modules as well as signals directly from registers. We efficiently generate possible templates considering dependence of instructions each of which invokes one or more data transfers between registers. The method also generates multiple templates in effective order to detect faults, which may cover different input spaces, and therefore, different detectable fault sets.
Keywords :
automatic test pattern generation; built-in self test; circuit analysis computing; high-speed integrated circuits; integrated circuit testing; microprocessor chips; shift registers; adjacent registers; data transfers; detectable fault sets; fault detection; instruction-based self-test; module under test; processor cores; template generation; test patterns; test program template; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Microprocessors; Performance evaluation; Registers; Test pattern generators;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.39