Title :
On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process
Author :
Ker, Ming-Dou ; Chiu, Po-Yen ; Tsai, Fu-Yi ; Chang, Yeong-Jar
Author_Institution :
Dept. of Electron. Eng., I-Shou Univ., Kaohsiung, Taiwan
Abstract :
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25degC in the silicon chip. Moreover, it can achieve ESD robustness of over 8 kV in human-body-model (HBM) and 750 V in machine-model (MM) ESD tests, respectively.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit testing; leakage currents; network synthesis; current 228 nA; gate leakage current; human-body-model; low-leakage power-rail electrostatic discharge clamp circuit; low-voltage CMOS process; machine-model ESD tests; power-rail ESD clamp circuit design; silicon chip; temperature 25 C; voltage 750 V; CMOS process; Circuits; Clamps; Electrostatic discharge; Gate leakage; Leakage current; MOS capacitors; Protection; Thyristors; Variable structure systems;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118254
