Title :
Optimum area minimization for nonslicing floorplan [VLSI layout]
Author :
Wang, Kai ; Chen, Wai-Kai
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
Abstract :
In this paper, we propose a new algorithm to solve the floorplan area optimization problem for all implementations of each module. By using slicing and extended slicing techniques, we decompose a complicated floorplan into basic L-shape and rectangular blocks in top-down manner and then combine them in bottom-up manner. Experimental results show that our algorithm is very efficient and capable of handling large floorplan compared to some existing ones
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; minimisation; L-shape blocks; VLSI layout; bottom-up combination; floorplan area optimization problem; nonslicing floorplan; rectangular blocks; top-down decomposition; Constraint optimization; Costs; Energy consumption; Integrated circuit technology; Minimization methods; Process design; Routing; Topology; Very large scale integration; Wheels;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343005
