Advanced process control for 40 nm gate fabrication

We developed a new APC technique, available to achieve no pattern-layout-dependence, for reducing lot-to-lot post-etch gate-CD variation and tracking them on a target for 40 nm gate fabrication. The model equation, adapted in our APC system, was a linear equation of gate CD loss as a function of SO₂/O₂ mixture ratio at a constant over etch time. It had a 10 nm of controllable range of gate CD etching loss with the its iso-to-dense difference within ±1 nm.