SiGe bipolar transistor modeling for a full chip ESD simulation

Author

Parthasarathy, Srivatsan ; Coram, Geoffrey J. ; Salcedo, Javier A. ; Hajjar, Jean-Jacques

Author_Institution

Analog Devices, Wilmington, MA, USA

fYear

2009

fDate

12-14 Oct. 2009

Firstpage

103

Lastpage

106

Abstract

A new compact model compatible with industry standard circuit simulation tools is developed to predict the current and voltage characteristics of SiGe bipolar transistors beyond their breakdown. This is a region of interest for circuit simulations during ESD (electro-static discharge) events. The enhanced bipolar models are benchmarked versus device-level TLP (transmission line pulse) measurements and used in full-chip ESD event simulation for identifying design weaknesses and optimizing emerging circuit designs for ESD robustness.

Keywords

Ge-Si alloys; bipolar transistors; circuit simulation; electrostatic discharge; network synthesis; ESD simulation; SiGe; bipolar transistor modeling; circuit designs; circuit simulation; electro-static discharge; transmission line pulse; Bipolar transistors; Breakdown voltage; Circuit simulation; Distributed parameter circuits; Electrostatic discharge; Germanium silicon alloys; Predictive models; Pulse measurements; Silicon germanium; Standards development; Compact modeling; Electrostatic Discharge; Electrostatic Discharge Simulation; SiGe bipolar transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE

Conference_Location

Capri

ISSN

1088-9299

Print_ISBN

978-1-4244-4894-4

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2009.5314133

Filename

5314133