A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs

Author

Kitahara, H. ; Tsukihara, T. ; Sakai, M. ; Morioka, J. ; Deguchi, K. ; Yonemura, K. ; Kikuchi, T. ; Onoue, S. ; Shirai, K. ; Watanabe, K. ; Kimura, K.

Author_Institution

Toshiba Semicond. Co., Oita, Japan

fYear

2009

fDate

12-14 Oct. 2009

Firstpage

206

Lastpage

209

Abstract

This paper presents a 0.13 um BiCD process (BiCD-0.13) based on a 0.13 um standard CMOS technology with a superior Deep Trench Isolation(DTI). Merits of using DTI are to improve breakdown voltage, reduce parasitic transistor actions and increase area density, compared with Junction-Isolation. We simulated the stress and the device characteristics, and optimized the parameters of DTI design and process steps. It has been successfully developed the process integration of DTI into 0.13 um process technology with various kinds of HV devices including ultra-low on resistance LDMOS.

Keywords

BiCMOS analogue integrated circuits; isolation technology; power integrated circuits; BiCD process technology; BiCMOS process technology; CMOS technology; analog power IC; deep trench isolation; resistance LDMOS; size 0.13 mum; Analog integrated circuits; Automotive engineering; CMOS process; CMOS technology; Costs; Diffusion tensor imaging; Diodes; Isolation technology; Power integrated circuits; Voltage; Deep Trench Isolation; LDMOS; Silicon bipolar/BiCMOS process technology; power devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE

Conference_Location

Capri

ISSN

1088-9299

Print_ISBN

978-1-4244-4894-4

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2009.5314160

Filename

5314160