Title :
A single-motion-vector/cycle-generation optical flow processor employing directional-edge histogram matching
Author :
Fujita, Kazuhide ; Ito, Kiyoto ; Shibata, Tadashi
Author_Institution :
Dept. of Frontier Inf., Univ. of Tokyo, Tokyo, Japan
Abstract :
A VLSI optical flow processor capable of generating a single motion vector at every clock cycle has been developed. By employing a directional-edge histogram matching, the computational cost has been reduced and the influence of illumination change has been alleviated as well. In order to generate an edge histogram in a single clock cycle, a special data allocation scheme in on-chip SRAM banks has been developed. In addition, a parallel shift and matching architecture using compact absolute difference circuits has been introduced. As a result, single-motion-vector/cycle generation from an arbitrary pixel location has been established. A prototype chip was fabricated in a 0.18-mum 5-metal CMOS technology and the measurement results demonstrated about 1,000 times faster performance at a clock frequency of 20 MHz than the software processing using a 2.8-GHz CPU.
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; image matching; image motion analysis; image resolution; image sequences; CMOS technology; CPU; VLSI optical flow processor; computational cost; data allocation scheme; directional-edge histogram matching; frequency 2.8 GHz; frequency 20 MHz; onchip SRAM banks; single-motion-vector-cycle-generation optical flow processor; software processing; CMOS technology; Circuits; Clocks; Computational efficiency; Computer architecture; Histograms; Image motion analysis; Lighting; Random access memory; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118439