• DocumentCode
    2267264
  • Title

    Reduce Leakage Currents in Low Power SRAM Cell Structures

  • Author

    Anand P, Rajeev ; Sekhar, Chandra

  • Author_Institution
    E.C.E. (Dept), Osmania Univ., Hyderabad, India
  • fYear
    2011
  • fDate
    26-28 May 2011
  • Firstpage
    33
  • Lastpage
    38
  • Abstract
    Two static random access memory cells that reduce the static power dissipation due to gate and sub threshold leakage currents are presented. The first cell lowers the leakage currents by using transmission gate and changes in ground level. Second cell lowers the leakage currents using dual-VTH and transmission gate. The whole project is implemented in CMOS 90nm technology.
  • Keywords
    CMOS logic circuits; SRAM chips; leakage currents; CMOS technology; dual-VTH; leakage current reduction; low power SRAM cell structure; static power dissipation; static random access memory cell; transmission gate; Layout; Leakage current; Logic gates; MOSFETs; Power dissipation; Random access memory; Dual threshold; gate leakage; low-power; static power; static random access memory (SRAM) cell;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing with Applications Workshops (ISPAW), 2011 Ninth IEEE International Symposium on
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4577-0524-3
  • Electronic_ISBN
    978-0-7695-4429-8
  • Type

    conf

  • DOI
    10.1109/ISPAW.2011.62
  • Filename
    5951946
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2267264