DocumentCode :
2268279
Title :
Advances of the counterflow pipeline microarchitecture
Author :
Janik, Kennneth J. ; Lu, Shih-Lien ; Miller, Michael F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fYear :
1997
fDate :
1-5 Feb 1997
Firstpage :
230
Lastpage :
236
Abstract :
The counterflow pipeline concept was originated by R.F. Sproull et al. (1994) to demonstrate the concept of asynchronous circuits. This architecture provides better throughput via clocking and data locality within the pipeline. We have taken these ideas and reformulated them into a scalable architecture that has the same locality for clocking and data, but adds aggressive speculation, fewer pipeline stalls, and a much faster startup. A high level C++ simulator has been built to explain the design tradeoffs. A VHDL model of an implementation of CFPP has been designed to validate the concept
Keywords :
instruction sets; parallel architectures; pipeline processing; VHDL model; asynchronous circuits; clocking; counterflow pipeline microarchitecture; data locality; design tradeoffs; high level C++ simulator; scalable architecture; throughput; Asynchronous circuits; Clocks; Hardware; Helium; Microarchitecture; Pipelines; Processor scheduling; Registers; Throughput; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 1997., Third International Symposium on
Conference_Location :
San Antonio, TX
Print_ISBN :
0-8186-7764-3
Type :
conf
DOI :
10.1109/HPCA.1997.569675
Filename :
569675
Link To Document :
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