DocumentCode
2268396
Title
Functional clock schedule optimization
Author
Aldanha, Alexander S. ; Shenoy, Narendra V. ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution
California Univ., Berkeley, CA, USA
fYear
1995
fDate
4-7 Jan 1995
Firstpage
93
Lastpage
98
Abstract
All existing algorithms for clock schedule optimization are conservative since they use only topological analysis to estimate the delays of paths between latches. This paper proposes a novel algorithm that accounts for false paths (over several time frames) in level-sensitive sequential circuits to obtain tighter bounds on the optimum clock schedule than previously obtainable
Keywords
circuit optimisation; clocks; delays; flip-flops; scheduling; sequential circuits; timing; clock schedule optimization; delays; false paths; latches; level-sensitive sequential circuits; time frames; Algorithm design and analysis; Clocks; Delay estimation; Flip-flops; Latches; Logic circuits; Optimal scheduling; Processor scheduling; Scheduling algorithm; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512084
Filename
512084
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