A 22Gb/s VCSEL driver using emphasis technique for ringing correction in 3rd-order RLC network

This article presents the design of a driver system for vertical cavity surface emitting lasers (VCSELs), including limiting amplifier, delay circuit, driver circuit and 5-bits DAC. By adding a delayed pulse on the original data signal, the VCSEL driver adopts a new method to compensate the ringing generated by the bound-wire inductance, pad capacitance and VCSEL. Through adjusting the delay time, width and height of the pulse, the technique can compensate the ringing effectively. The proposed circuit adopts TSMC 65nm CMOS technology. The results of post simulation demonstrate that good eye opening and a peak-to-peak jitter less than 5ps can be attained when the system works up to 22Gb/s. The total power consumption is less than 70mW with 1V and 3.3V power supplies.