Title :
A single chip, pipelined, cascadable, multichannel, signal processor
Author :
Krishnakumar, S. ; Suresh, P. ; Rao, S. Sadashiva ; Pareek, M.P. ; Gupta, Rajat
Author_Institution :
TI, Bangalore, India
Abstract :
The architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. This paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. The signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL´s 2μm double metal CMOS process and packaged in a 144 pin CPGA
Keywords :
Adders; Array signal processing; Delay lines; Digital signal processing chips; Digital signal processors; Filter bank; Finite impulse response filter; Pipeline processing; Signal processing; Transfer functions;
Conference_Titel :
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-6905-5
DOI :
10.1109/ICVD.1995.512095