VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes

The paper introduces an extension to previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed approach constructs systematic odd-weight-column SEC-DED-SBD codes whose corrigible errors also include any odd number of erroneous bits per byte. The main purpose of this paper is to show that the proposed codes are suitable for high performances VLSI implementations in computer applications, using high speed encoding/decoding circuits and parallel data manipulation. Furthermore, the paper shows how such codes can be easily designed from the specifications using a software tool, which generates the VHDL (VHSIC Hardware Description Language) description of the circuits