Automatic structuring and optimization of hierarchical designs

In this paper an approach for the optimization of digital synchronous designs is described. The optimization is done for smaller components which are the result of a partitioning process. The actual optimization is done on a graph which reflects the communication structure between the modules. Sequential don´t care conditions are extracted and used for sequential optimization. As experimental results show, the robustness of the subsequent logic synthesis methods can be increased while achieving a significant gain in cost and power consumption. This is shown by applying the described methods to a set of benchmarks obtained from high-level synthesis