Ultra-Low-Power 500-MSPS 12-bit A/D Converter Using Interleaving and CMOS Charge-Domain Technology

Author

Anthony, Michael P. ; Sollner, G.

Author_Institution

Intersil Corp., Woburn, MA, USA

fYear

2009

fDate

11-14 Oct. 2009

Firstpage

1

Lastpage

4

Abstract

A 12-bit analog-to-digital converter (ADC) has been developed using a unique charge-domain method of handling the analog signals. By interleaving two 250-MS/s unit ADCs on a single chip, an aggregate sample rate of 500 MS/s is achieved. Performance is comparable or superior to all existing ADCs at this sample rate, with power consumption less than 1/5^th of that needed by other available designs. Signal-to-noise ratio (SNR) of 65.6 dBFS and spurious-free dynamic range (SFDR) of 78 dBc are obtained at an input frequency of 250 MHz. Total power consumption is 432 mW from a single 1.8-V supply. Added sampling jitter is 60 fs.

Keywords

CMOS integrated circuits; analogue-digital conversion; A/D converter; CMOS charge-domain technology; analog signal; analog-to-digital converter; charge-domain method; complementary metal-oxide-semiconductor; frequency 250 MHz; interleaving; power 432 mW; sampling jitter; signal-to-noise ratio; single chip; spurious-free dynamic range; Aggregates; Analog-digital conversion; CMOS technology; Dynamic range; Energy consumption; Frequency; Interleaved codes; Jitter; Sampling methods; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2009. CISC 2009. Annual IEEE

Conference_Location

Greensboro, NC

ISSN

1550-8781

Print_ISBN

978-1-4244-5191-3

Electronic_ISBN

1550-8781

Type

conf

DOI

10.1109/csics.2009.5315608

Filename

5315608