Quasi-static energy recovery logic and supply-clock generation circuits

A Quasi-Static Energy Recovery Logic family (QSERL) using two complementary sinusoidal supply clocks is proposed in this paper. A high-efficiency clock generation circuitry which generates two complementary sinusoidal clocks required by QSERL is also presented. The clock circuitry locks both frequency and phase of clock signals, which makes it possible to integrate adiabatic module into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 37% of energy over static CMOS multiplier at 100 MHz.