DocumentCode
2270932
Title
Intel’s Post Silicon functional validation approach
Author
Tommy, Bojan ; Igor, Frumkin ; Robert, Mauri
Author_Institution
Intel Corp., Haifa
fYear
2007
fDate
7-9 Nov. 2007
Firstpage
53
Lastpage
56
Abstract
CPU Post-Silicon functional validation is the last "guardian" logic-wise before delivering the product to the market. In each CPU generation, the challenges are larger due to increasingly complex architectures, budget constraints and shorter schedules. Success can be achieved just with the novel approaches across different validation teams, and with a complex of state-of-the-art validation software, hardware, execution and silicon debug environments. Budget constraints lead to high automation and efficient validation process. Though Intel Corporation has different divisions, mutual help and hard work and optimization ensures high quality product within the schedule.
Keywords
formal verification; logic design; logic testing; microprocessor chips; CPU generation; Intel Corporation; complex architecture; corner-case bugs; post silicon functional validation; product quality; silicon debug environment; Computer bugs; Controllability; Debugging; Energy management; Job shop scheduling; Manufacturing; Prototypes; Silicon; Temperature dependence; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International
Conference_Location
Irvine, CA
ISSN
1552-6674
Print_ISBN
978-1-4244-1480-2
Type
conf
DOI
10.1109/HLDVT.2007.4392786
Filename
4392786
Link To Document