DocumentCode
2272030
Title
Architectural support for reducing communication overhead in multiprocessor interconnection networks
Author
Dao, Binh Vien ; Yalamanchili, Sudhakar ; Duato, Jose
Author_Institution
Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
1997
fDate
1-5 Feb 1997
Firstpage
343
Lastpage
352
Abstract
Modern multicomputer interconnection networks offer the delivery of messages with very low latency. However the message in-flight time is only a small portion of the total time that is required to send a message from source to destination. For fine to medium grained message sizes, the majority of time is spent in overheads for setting up and managing message transmission. It is often possible for compilers/programmers to separate inter-processor communication traffic into messages that exhibit communication locality and messages that do not. This paper proposes architectural modifications to network interfaces and routers to enable compilers/programmers to exploit known locality properties of programs in reducing the fixed overhead of transmission. These techniques work well on traffic exhibiting communication locality without unduly penalizing “ordinary” message traffic. The proposed techniques are evaluated using communication traces from 5 application program kernels. Significant reductions in average message latency are possible, and we argue that the approach can be used in the next generation of cluster interconnects
Keywords
message passing; multiprocessor interconnection networks; network interfaces; application program kernels; architectural support; cluster interconnects; communication locality; communication overhead reduction; communication traces; inter-processor communication traffic; message in-flight time; multiprocessor interconnection networks; network interfaces; routers; Circuits; Communication switching; Delay; Electronic mail; Intelligent networks; Message passing; Modems; Multiprocessor interconnection networks; Network interfaces; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 1997., Third International Symposium on
Conference_Location
San Antonio, TX
Print_ISBN
0-8186-7764-3
Type
conf
DOI
10.1109/HPCA.1997.569699
Filename
569699
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