Hypercomputers: design and architecture

The authors introduce the Hypercomputer supercomputer, a reconfigurable, massively parallel architecture, a 9,072 processor prototype currently planned. The hypercomputer architecture family is based on arrays of a simple and autonomous unit logic entity, the universal cell. Physically wired in a uniform, eight-degree mesh, the universal cell is pipelined, 8-bit microarchitecture that provides the logical manifestation of processor elements, switch lattices, memory units, et cetera. In this sense, the hypercomputer family is honeycomb reconfigurable. The mesh array is supported by a separate 3D, parallel IO network which provides real-time IO in the planar dimension and distributed configuration and synchronization along the polar dimension. The programming model, is based on a new concept, computational holism, whereby increasingly abstract and logically seamless clusters of tightly coupled cell chunks or actors give rise to parallel and highly specialized centers of computational activity. The software realization of this holistic approach is embodied in hyperware, an object-oriented, visually interactive environment for composing algorithmically specialized actors